Two types of semiconductor memory devices are a random access memory (RAM) and a read only memory (ROM). The RAM devices provide a volatile memory that can include a dynamic random access memory (DRAM) and/or a static random access memory (SRAM), both of which lose data upon a loss of power, but can provide relatively fast write/read operations. In contrast, the ROM devices provide a non-volatile memory that can retain data upon a loss of power, but can provide relatively slower write/read operations. Non-volatile memory devices can have an almost permanent data retention capacity. One type of the non-volatile memory device is a flash memory, such as an electrically erasable and programmable ROM (EEPROM). The EEPROMs are widely used in memory devices because they allow both reading and writing of data.
The flash memory devices can be categorized as a NAND type and a NOR type devices based on their circuitry. In the NAND type flash memory device, a number of cell transistors are connected in series to form a unit string, and these unit strings are connected in parallel between a bit line and a ground line. In the NOR type flash memory device, the respective cell transistors are coupled in parallel between the bit line and the ground line. In a comparison of the NOR and the NAND type devices, the NOR type devices can provide relatively higher-speed operation and the NAND type devices can allow higher integration density.
The flash memory cell can have a vertical gate structure, which includes a floating gate formed on a silicon substrate. The multi-layered gate structure typically includes at least one tunnel oxide layer or dielectric layer, and a control gate formed on or near the floating gate.
In the multi-layered gate structure of the NAND type flash memory cell, the floating gates are usually located in the active region with a linear structure. The floating gates should be formed on the active region with at least a defined size that is sufficient to maintain an adequate cell current and coupling ration. However, as the size of memory cells becomes increasingly smaller, the area of the active region also becomes smaller and the area on which the floating gate can be formed also decreases. As a result, Fower-Nordheim (F-N) tunneling may not properly occur during operation on a memory cell because of, for example, decreased cell current and deterioration in the distribution characteristics of the tunneling.
In Japanese Patent Laid-open Publication No. 2002-33476, a field region is wet-etched to expand the active region after finishing an element isolation process that defines an active region. Although the area of the active region may be increased, the increase appears to be very small relative to the reduction in the thickness of the field region, as the result of the wet etching process.